epic defines a new style of architecture that enables higher levels of instruction level parallelism ( ilp ) without unacceptable hardware complexity epic是一种显性并行指令计算体系结构,主要思想是利用编译器和处理器的协同能力来提高指令级并行度。
state-of-the-art microprocessors exploit instruction level parallelism ( ilp ) to achieve high performance on applications by searching for independent instructions in a dynamic window of instructions and executing them on a wide-issue pipeline 对于当前软件中占主要部分的串行程序而言,微处理器主要依靠开发程序的指令级并行(ilp)来提高性能。
multithreaded microprocessor, which has many hardware contexts sharing an execution core, can efficiently exploit both the instruction level parallelism and thread level parallelism to acquire higher performance and better performance / power ratio 多份硬件现场共享一组执行单元的多线程处理器能灵活地利用程序中的指令级并行和线程级并行,从而提供更好的性能。
one of the key elements to achieving higher performance in microprocessors is executing more instructions per cycle . however, dependencies among instructions, varying latencies of certain instructions, and execution resources constraints, limit this parallelism considerably . in order to exploit instruction level parallelism, processor should employ data dependence analysis to identify independent instructions that can execute in parallel 当前,在微处理器体系结构研究中,为了充分提高微处理器的处理性能,主要采用了指令级并行技术(ilp),指令级并行性的开发程度对发挥微处理器的硬件特性,提高程序运行性能至为关键。